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Verilog source code  |  1992-06-18  |  507 b   |  24 lines  |  [TEXT/MPS ]
  1. module alu(op, d, s1, s2);
  2.  
  3.     input     [ 4: 0]op;
  4.     input    [31: 0]s1,
  5.                     s2;
  6.     output   [31: 0]d;
  7.     
  8.     assign    d = (op == 0 || op == 9 ?    s1+s2:
  9.                  op == 1?                s1-s2:
  10.                  op == 2?                s1&s2:
  11.                  op == 3?                s1|s2:
  12.                  op == 4?                s1^s2:
  13.                  op == 5?                s1<s2:
  14.                  op == 6?                s1<=s2:
  15.                  op == 7?                s1==s2:
  16.                  op == 8?                (s2[31]?s1<<s2:s1>>(-s2)):
  17.                  op == 16?                s1:
  18.                  op == 17?                s2:
  19.                  op == 18?                {s2[15:0],s1[15:0]}:
  20.                                          0);
  21.                                         
  22.  
  23. endmodule
  24.